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FINAL
COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all GAL s s
Advanced Micro Devices
s Peripheral Component Interconnect (PCI)
s s s
20V8/As Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology -- 5-ns propagation delay for "-5" version -- 7.5-ns propagation delay for "-7" version Direct plug-in replacement for a wide range of 24-pin PAL devices Programmable enable/disable control Outputs individually programmable as registered or combinatorial
compliant
s Preloadable output registers for testability s Automatic register reset on power-up s Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
s Extensive third-party software and programmer
support through FusionPLD partners
s Fully tested for 100% programming and func-
tional yields and high reliability
s Programmable output polarity s 5-ns version utilizes a split leadframe for
improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices. Device logic is automatically configured according to the user's design specification. A design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming file based on Boolean or state equations. Design software also verifies the design and can provide test vectors for the finished device. Programming can be accomplished on standard PAL device programmers. The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
BLOCK DIAGRAM
10
I1 - I10
CLK/I0
Programmable AND Array 40 x 64
Input Mux.
MACRO MC0
MACRO MC1
MACRO MC2
MACRO MC3
MACRO MC4
MACRO MC5
MACRO MC6
MACRO MC7
Input Mux.
OE/I11 I12
Publication# 16491 Rev. D Issue Date: February 1996
I/O0
I/O1
I/O2
I/O4
I/O4
I/O5
I/O6
I/O7
I13
16491D-1
Amendment /0
2-155
AMD
CONNECTION DIAGRAMS (Top View) SKINNYDIP
CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I13 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I12 OE/I11
16491D-2
PLCC/LCC
CLK/I0 NC VCC I/O7 25 24 23 22 21 20 19 12 13 14 15 16 17 18 GND NC OE/I11 I12 I/O0
16491D-3
4 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11
3 2 1 28 27 26 I/O6 I/O5 I/O4 NC I/O3 I/O2 I/O1
Note: Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK GND I I/O NC OE VCC = Clock = Ground = Input = Input/Output = No Connect = Output Enable = Supply Voltage
2-156
PALCE20V8 Family
I9 I10
I13
I2 I1
AMD
ORDERING INFORMATION Commercial and Industrial Products
AMD programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
PAL FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF FLIP-FLOPS POWER H = Half Power (90-125 mA ICC) Q = Quarter Power (55 mA ICC) SPEED -5 = 5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD -25 = 25 ns tPD
CE
20 V 8 H -5 P C /5
PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 Second Revision (Same algorithm as /4) OPERATING CONDITIONS C = Commercial (0C to +75C) I = Industrial (-40C to +85C)
PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
Valid Combinations PALCE20V8H-5 JC /5 PALCE20V8H-7 Blank, /4 PALCE20V8H-10 PC, JC /5 PALCE20V8Q-10 PALCE20V8H-15 PC, JC, PI, JI PALCE20V8Q-15 PC, JC Blank, /4 PALCE20V8Q-20 PI, JI PALCE20V8H-25 PC, JC, PI, JI PALCE20V8Q-25
Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com'l) PALCE20V8H-15/25, Q-20/25 (Ind)
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AMD
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells (MC0..MC7). Each macrocell can be configured as a registered output, combinatorial output, combinatorial I/O, or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE20V8 are automatically configured from the user's design specification, which can be in a number of formats. The design
specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user's desired function. The user is given two design options with the PALCE20V8. First, it can be programmed as an emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL devices. The PAL device programmer manufacturer will supply device codes for the standard PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8 to the corresponding PAL device architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This option provides full utilization of the macrocells, allowing non-standard architectures to be built.
11 0X 10
OE VCC
1 1 0 0
1 0 0 1
To Adjacent Macrocell
SL0X SG1 11 0X D SL1X CLK Q Q 10 11 0X *SG1 SL0X 10 I/OX
From Adjacent Pin
16491D-4
* In Macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
Figure 1. PALCE20V8 Macrocell
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Configuration Options
Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, the buffer is always disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent I/O. The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell and SL1x sets the output as either active low or active high. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. These configurations are summarized in table 1 and illustrated in figure 2. If the PALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be used as data inputs.
Dedicated Output in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.
Dedicated Input in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The feedback signal is an adjacent I/O pin.
Combinatorial I/O in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Table 1. Macrocell Configurations
SG0 SG1 SL0x Cell Configuration Devices Emulated Device has registers 0 0 1 1 0 1 Registered Output Combinatorial I/O PAL20R8, 20R6, 20R4 PAL20R6, 20R4
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the flipflop. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE.
Device has no registers 1 1 1 0 0 1 0 1 1 Combinatorial Output Dedicated Input Combinatorial I/O PAL20L2, 18L4,16L6,14L8 PAL20L2,18L4, 16L6 PAL20L8
Combinatorial Configurations
The PALCE20V8 has three combinatorial output configurations: dedicated output in a non-registered device, I/O in a non-registered device and I/O in a registered device.
Programmable Output Polarity
The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts. Selection is made through a programmable bit SL1x which controls an exclusive-OR gate at the output of the AND/OR logic. The output is active high if SL1x is a 0 and active low if SL1x is a 1. PALCE20V8 Family 2-159
AMD
OE OE
D CLK
Q Q CLK
D
Q Q
Registered Active Low
Registered Active High
Combinatorial I/O Active Low
Combinatorial I/O Active High
VCC
VCC
Note 1
Note 1
Combinatorial Output Active Low
Combinatorial Output Active High
Notes: 1. Feedback is not available on pins 18 (21) and 19 (23) in the combinatorial output mode. 2. This macrocell configuration is not available on pins 18 (21) and 19 (23).
Note 2
Adjacent I/O pin
Dedicated Input Figure 2. Macrocell Configurations 2-160 PALCE20V8 Family
16491D-5
AMD
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic.
Programming and Erasing
The PALCE20V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required.
Quality and Testability
The PALCE20V8 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming and post-programming functional yields in the industry.
Register Preload
The register on the PALCE20V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery.
Technology
The high-speed PALCE20V8H is fabricated with AMD's advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching.
Security Bit
A security bit is provided on the PALCE20V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle.
PCI Compliance
The PALCE20V8H-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE20V8H-7/10's predictable timing ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution.
Electronic Signature Word
An electronic signature word is provided in the PALCE20V8. It consists of 64 bits of programmable memory that can contain any user-defined data. The signature data is always available to the user independent of the security bit.
PALCE20V8 Family
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AMD
LOGIC DIAGRAM SKINNYDIP (PLCC and LCC) Pinouts
0
34
78
11 12
15 16 19 20
23 24 27 28
31 32 35 36 39
CLK/I0 1 (2) I1 2 (3)
1 0
24 VCC (28) 23 (27) VCC
11 10 00 01
I 13
SG0
11 0X 10
0
SL0 7 SG1
D Q Q 10 11 0X 11 0X 10
22 I/O7 (26)
7
I2 3 (4)
SG0
SL07
11 0X 10
VCC
11 10 00 01
8
SL06 SG1
D Q Q 10 11 0X 11 0X 10
21 I/O6 (25)
15
I3 4 (5)
SG1
SL06
11 0X 10
VCC
11 10 00 01
16
SL05 SG1
D Q Q 10 11 0X 11 0X 10
20 I/O5 (24)
23
I4 5 (6)
SG1
SL05
11 0X 10
VCC
11 10 00 01
24
SL04 SG1
D Q Q 10 11 0X 11 0X 10
19 I/O4 (23)
31
I5 6 (7)
SG1
SL04
0
34
78
11 12 15 16 19 20 23 24 27 28
31 32 35 36 39
CLK OE
16491D-6
2-162
PALCE20V8 Family
AMD
LOGIC DIAGRAM (continued) SKINNYDIP (PLCC and LCC) Pinouts
0
34
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39
CLK OE
11 10 00 01
11 0X 10
VCC
32
SL03 SG1
D Q Q 10 11 0X 11 0X 10
18 I/O3 (21)
39
I6 7 (9)
SG1
SL0 3
11 0X 10
VCC
11 10 00 01
40
SL02 SG1
D Q Q 10 11 0X 11 0X 10
17 I/O2 (20)
47
I7 8 (10)
SG1
SL02
11 0X 10
VCC
11 10 00 01
48
SL01 SG1
D Q Q 10 11 0X 11 0X 10
16 I/O 1 (19)
55
I8 9 (11)
SG1
SL01
11 0X 10
VCC
11 10 00 01
56
SL00 SG1
D Q Q 10 11 0X 11 0X 10
15 I/O0 (18)
63
I 9 10 (12)
SG0
SL00
10 11 (13)
0 1
SG0
14 I12 (17) 13 OE/I11 (16)
0
34
78
11 12 15 16 19 20
23 24 27 28 31 32
35 36
39
16491D-6 (concluded)
PALCE20V8 Family
2-163
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +75C) . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Conditions IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min VIN = VIH or VIL VIN = VIH or VIL 2.0 0.8 10 -100 10 -100 -30 H Q -150 90 55 Min 2.4 0.5 Max Unit V V V V A A A A mA mA
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz
Notes: 1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
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AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 5 8 Unit pF pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH fMAX tPZX tPXZ tEA tER Clock Width Maximum Frequency (Note 3) -15 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input or Feedback to Clock Hold Time Clock to Output LOW HIGH External Feedback Internal Feedback (fCNT) No Feedback 1/(tS + tCO) 1/(tS + tCF) (Note 4) 1/(tWH + tWL) 8 8 45.5 50 62.5 15 15 15 15 12 0 10 12 12 37 40 41.6 20 20 25 25 Min Max 15 15 0 12 Min -25 Max 25 Unit ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
OE to Output Enable OE to Output Disable Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALCE20V8H-15/25 Q-15/25 (Com'l)
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AMD
SWITCHING WAVEFORMS
Input or Feedback tS Input or Feedback VT tPD Combinatorial Output VT
16491D-7
VT tH VT tCO
Clock
Registered Output
VT
16491D-8
Combinatorial Output
Registered Output
tWH Clock tWL
16491D-9
Input VT Output tER VOH - 0.5V VOL + 0.5V
VT tEA VT
16491D-10
Clock Width
Input to Output Disable/Enable
VT OE tPXZ Output VOH - 0.5V VOL + 0.5V tPZX VT
16491D-11
OE to Output Disable/Enable
Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns - 5 ns typical.
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KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply
OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V S1
R1
Output R2
CL
Switching Test Circuit
Commercial Specification tPD, tCO tPZX, tEA tPXZ, tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 50 pF 5 pF 200 CL R1
16491D-12
R2
Measured Output Value 1.5 V
390 H-5: 200
1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
PALCE20V8 Family
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TYPICAL ICC CHARACTERISTICS VCC = 5.0 V, TA = 25C
150
125
20V8H-5
100
20V8H-7 ICC (mA) 75 20V8H-10 20V8H-15/25
50 20V8Q-10 20V8Q-15/25
25
0 0 10 20 30 40 50
16491D-13
Frequency (MHz)
ICC vs. Frequency
The selected "typical" pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design.
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ENDURANCE CHARACTERISTICS
The PALCE20V8 is manufactured using AMD's advanced electrically erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed--a feature which allows 100% testing at the factory.
Endurance Characteristics
Symbol tDR N Parameter Min Pattern Data Retention Time Min Reprogramming Cycles Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions Min 10 20 100 Unit Years Years Cycles
PALCE20V8 Family
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POWER-UP RESET
The PALCE20V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below.
Parameter Symbol tPR tS tWL Parameter Description Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are:
s The VCC rise must be monotonic. s Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feedback setup times are met.
Min Max 1000 See Switching Characteristics Unit ns
4V Power
VCC tPR
Registered Output
tS
Clock
tWL
16491D-16
Power-Up Reset Waveforms
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PALCE20V8 Family

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